Performance Evaluation of Queue Processors vs Risc Architecture

Performance Evaluation of Queue Processors vs Risc Architecture.

ABSTRACT  

Nowadays, shifts in Hardware and Software technologies have forced designers and users to look at micro-architecture that process instructions stream with high performance and low power consumption. In Striving for such high performance, the Queue Processor has been designed with architecture which has the following features:  

• Low power consumption  
• Smaller code size  
• Simple Hardware  
• High Performance in terms of Speed  
• High Instruction level parallelism  

This research aims at comparing and evaluating these performance features of the Queue Processor architecture with the traditionally used RISC architecture. Evaluation will be done in terms of Software (code size, execution time) and Hardware (Logical Elements, power and speed). This evaluation is performed using Quartus II IDE by Altera.

The QSoC will be used as case study for the Queue Processor while Aquarius will be used as case study for the RISC processor. I’m confident that this evaluation research will show a significant improvement in the performance of the Queue Processor over the RISC Architecture. 

TABLE OF CONTENTS

CHAPTER 1 – INTRODUCTION……………………………………………………………………………………1
1.1 Importance of Performance Evaluation …………………………………………………………………….1
1.2 Research Objectives……………………………………………………………………………..2
1.3 Motivation of Research……………………………………………………………………2
1.4 Queue Computing…………………………………………………………………………3
1.5 Thesis Outline……………………………………………………………………………..4

CHAPTER 2 –LITERATURE REVIEW…………………………………………………………………………5
2.1 A Short History of Processor Architecture ………………………………………………………………..5
2.2 Measuring Processor Performance………………………………………………………..6
2.3 Conventional Processor……………………………………………………………………7
2.3.1 Issues with Conventional Processors…………………………………………………………………….7
2.3.2 Architectural Techniques……………………………………………………………….7
2.4 Produced Order Queue Computing………………………………………………………..9
2.5 Queue Core Architecture…………………………………………………………………13
2.5.1 ALU (Arithmetic Logic Unit)……………………………………………………..…..13
2.5.2 MLT (Multiplier, Divider and MOD Instructions)……………………………………14
2.5.3 LOAD/STORE………………………………………………………………………..14
2.5.4 SET……………………………………………………………………………………15
2.5.5 Branch…………………………………………………………………………………15
2.6 Instruction Pipeline Structure……………………………………………………………16

CHAPTER 3 – QUEUE Vs RISC MACHINES………………………………………………23
3.1 Queue Machine Analysis…………………………………………………………………24
3.1.1 Higher Instruction Level Parallelism (ILP)…………………………………………..24
3.1.2 Reduced Instruction Width……………………………………………………………26
3.1.3 Free from False Dependencies………………………………………………………..27
3.1.3.1 Register Renaming……………………………………………………………….27
3.1.4 Drawbacks of Queue Machines…………………………………………………………29
3.2 QSoC Simulation and Synthesis…………………………………………………………30
3.3 Quartus II Overview……………………………………………………………………..30
3.4 FPGA Implementation of QSoC…………………………………………………………31
3.5 Pictorial Summary of Queue Machines Vs RISC Machines…………………………….32

CHAPTER 4 – COMPLEXITY ANALYSIS…………………………………………………34
4.1 Code Size…………………………………………………………………………………34
4.2 Synthesis Result (Logical Elements)…………………………………………………….36
4.3 Power and Speed Comparison Results…………………………………………………..37

CHAPTER 5 DISCUSSION OF RESULTS…………………………………………………….39

CHAPTER 6 CONCLUSION………………………………………………………………….40
6.1 Future Work………………………………………………………………………………40

REFERENCES …………………………………………………………………………………41

INTRODUCTION  

Performance evaluation is at the foundation of computer architecture research and development. Contemporary microprocessors are so complex that architects cannot design systems based on intuition and simple models only. Adequate performance evaluation methods are absolutely crucial to steer the research and development process in the right direction.

However, rigorous performance evaluation is nontrivial as there are multiple aspects to performance evaluation, such as picking workloads, selecting an appropriate modelling or simulation approach, running the model and interpreting the results using meaningful metrics. Each of these aspects is equally important and a performance evaluation method that lacks rigor in any of these crucial aspects may lead to inaccurate performance data and may drive research and development in a wrong direction.  

The major aims of Performance Evaluation are to: 

• Collect and disseminate information relative to performance aspects, and in particular to a specific topic. 
• Promote interdisciplinary flow of technical information among researchers and professionals. 
• Serve as a publication medium for various special interest groups in the performance community at large.

REFERENCES

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Quantitative Approach, Morgan Kaufmann Publishers Inc., 1990.

M. Fernandes, J. Llosa, N. Topham, Using queues for register file organization in VLIW,
Technical Report ECS-CSG-29-97, Department of Computer Science, University of
Edinburgh, 1997.

B.A. Abderazek, Dynamic instructions issue algorithm and a queue execution model
toward the design of hybrid processor architecture, Ph.D. Thesis, Graduate School of
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Lieven Eeckhout , Computer Architecture Performance Evaluation Methods, Synthesis
Lectures on Computer Architecture, June 2010, Vol. 5, No. 1, Pages 1-145

Martti Forsell, Implementation of Instruction-Level and Thread-Level Parallelism in
Computers, 1997.

B.A. Abderazek, Queue Machines: an unknown alternative – PDCAT 2009

B.A. Abderazek, M. Arsenji, S. Shigeta, T. Yoshinaga, M. Sowa, Queue processor for
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B.A. Abderazek, T. Yoshinaga, M. Sowa, High-level modeling and FPGA prototyping of
produced order parallel queue processor core, J. Supercomputing 38 (1) (2006) 3–15.s

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