Network – on – Chip (Noc) Communication Architecture.
Abstract
Network – On – Chip (NoC) communication architecture have emerged as a solution to problem of lack of scalability, clock delay, lack of support for concurrent communication and power consumption exhibited by the shared bus communication approach to System – On – Chip (SoC) implementations.
However, a NoC communication requirement such as bandwidth is affected by architecture parameters as topology, routing, buffer size etc.
In this project, we implement an adaptive approach of NoC to solve the problems of the static approach method such as routing delay, lack of flexibility and inability to predict dynamic behaviour of the applications.
The adaptive approach supports several applications by changing parameters at run – time.
Table Of Contents
Abstract iii
Dedication……………iv
Acknowledgments…………. v
Table of Contents…………………vi
Chapter 1 : Introduction
- Introduction to System On Chip……………… 1
- Emergence of Network On Chip (NOC)………..1
- Related Work……………………… 2
- Problems of NOC………………….3
- Topology 3
- Buffer Size 3
- Channel Width…………….3
- Routing 4
- Project Contribution……………..4
- Report Organization……………..5
Chapter 2 : Network On Chip
- Introduction…………………….. 6
- On – Chip System Interconnection Overview…… 7
- Bus – Based System…………….7
- The NOC – Based……………8
- NOC Designs Issues………….9
Chapter 3 :… OASIS Interconnection Network
- Introduction…………..15
- OASIS NoC Architecture…………..15
- Switching 16
- Routing 21
- Flow Control………. 24
Chapter 4 : OASIS With Run Time Monitoring System
- Introduction………… 26
- Algorithm………………27
- Architecture……………….. 32
- Algorithm Implementation in Hardware…………. 33
Chapter 5 : Hardware and Software Evaluation Results
- Hardware Complexity………..38
- Logic 38
- Power 39
- Speed 39
- Functional Simulation…………………….. 40
- Algorithm Verification………………… 40
- Packet Delay…………………………41
Chapter 6 : CONCLUSION
REFERENCES…………………..44
Introduction
Background Of Study
Complex applications, using System On Chips (SoCs) can be implemented by integrating more cores since the number of cores increases rapidly.
That is, the rapid development of cores technology allows complex circuits to be integrated into a single chip. This also means that the system’s complexity also increases; hence designers tend to keep up with the increased complexity by using larger reusable blocks in their system design.
However, with these different processing elements used together to achieve powerful systems, connecting these cores together posses a great challenge.
And as the number of these computational units/processing units increases and are integrated into one silicon chip, communication between them becomes a problem. A communication system that will support these cores must be designed.
Bus – based communication, where bus access request of nodes or cores are serialized through central arbiters, is a simple solution to the communication problem.
However, this simple approach presents numerous challenges like scalability problem, bus capacitance increases dramatically with increase bus length and more additional cores, performance penalties, inefficient power or energy as the number of cores increases.
References
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Mori, A. B. Abdallah, K. Kuroda. “Design and Evaluation of a Complexity Effective Network-on-Chip Architecture on FPGA”. The 19th Intelligent System Symposium (FAN 2009),pp.318-321, Sep. 2009.
A. Abderazek, M. Sowa. “Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization”. Proceedings of the tjassst2006 symposium on science, society and technology, sousse, dec. 4-6, 2006.
Liu. “Efficient Application Mapping and Scheduling for Networks-on- Chip”.Technical Report: Department of Computer Science and Engineering Hong Kong University of Science and Technology April 10, 2008 .
HU. “Design Methodologies for Application Specific Networks-On- Chip”. A PhD thesis submitted to the department of Electrical and Computer Engineering, Carnegie Mellon University USA, 2005.
Bjerregaard, S. Mahadevan. “A Survey of Research and Practices of Network-on-Chip” ACM Computing Surveys, Vol. 38, March 2006, Article 1.